Method for manufacturing semiconductor device

ABSTRACT

A lower resist ( 2 ) is applied on a semiconductor substrate ( 1 ). An upper resist ( 3 ) is applied on the lower resist ( 2 ). A first opening ( 4 ) is formed in the upper resist ( 3 ) by exposure and development and the lower resist ( 2 ) is dissolved with a developer upon the development to form a second opening ( 5 ) having a width wider than that of the first opening ( 4 ) below the first opening ( 4 ) so that a resist pattern ( 6 ) in a shape of an eave having an undercut is formed. Baking is performed to thermally shrink the upper resist ( 3 ) to bent an eave portion ( 7 ) of the upper resist ( 3 ) upward. After the baking, a metal film ( 8 ) is formed on the resist pattern ( 6 ) and on the semiconductor substrate ( 1 ) exposed at the second opening ( 5 ). The resist pattern ( 6 ) and the metal film ( 8 ) is removed on the resist pattern ( 6 ) and the metal film ( 8 ) is left on the semiconductor substrate ( 1 ) as an electrode ( 9 ).

FIELD

The present disclosure relates to a method for manufacturing asemiconductor device.

BACKGROUND

As a method for manufacturing a gate electrode or a wiring electrode ofa transistor, a liftoff process of depositing a metal film over a resistand then dissolving and removing the resist so that the metal film isleft only at an opening portion of the resist as an electrode isemployed. The liftoff process requires that a metal film deposited onthe resist be discontinuous with a metal film deposited on a foundationlayer at the opening portion of the resist.

In related art, a resist is formed in a reverse tapered shape using anegative resist or an image reversal resist. However, the reverse taperis not stable, and the metal film on the resist may become continuouswith the metal film at the opening portion of the resist, causing metalburrs and resulting in occurrence of a liftoff defect. To address this,a liftoff process involving forming a two-layer resist in a shape of aneave having an undercut has been proposed. This method makes a metalfilm on the resist discontinuous with a metal film at an opening portionof the resist, so that it is possible to prevent occurrence of metalburrs.

However, a side wall of an upper resist of the two-layer resist becomesperpendicular, and a metal grows in a columnar shape on the side wall.The columnar metal growing on the side wall spills over on a gateelectrode or on the periphery upon liftoff, which negatively affectsdevice characteristics and causes a problem of degradation of a defectrate. It is necessary to taper a side wall corner of the upper resist toprevent the metal from spilling over. However, a method of laminating aninsulating film and a one-layer resist to form a shape of an eave cannotbe applied to a structure in which an electrode is formed on theinsulating film. Thus, a resist formation method which tapers the upperresist of the two-layer resist is demanded. In response to this demand,a two-layer resist in which a positive resist and an image reverseresist are laminated has been proposed (see, for example, PTL 1).

CITATION LIST PATENT LITERATURE

[PTL n] JP H10-154707 A

SUMMARY Technical Problem

However, a shape of the upper resist is not stable and can be a reversetapered shape. Thus, a problem arises that it is impossible to stablyprevent a metal from spilling over in the liftoff process.

The present invention has been made to solve the problems as describedabove, and an object of the present invention is to provide a method formanufacturing a semiconductor device which is capable of stablypreventing a metal from spilling over in a liftoff process.

Solution to Problem

A method for manufacturing a semiconductor device according to thepresent disclosure includes: applying a lower resist on a semiconductorsubstrate; applying an upper resist on the lower resist; forming a firstopening in the upper resist by exposure and development and dissolvingthe lower resist with a developer upon the development to form a secondopening having a width wider than that of the first opening below thefirst opening so that a resist pattern in a shape of an eave having anundercut is formed; performing baking to thermally shrink the upperresist so that an eave portion of the upper resist is bent upward; afterthe baking, forming a metal film on the resist pattern and on thesemiconductor substrate exposed at the second opening; and removing theresist pattern and the metal film on the resist pattern and leaving themetal film on the semiconductor substrate as an electrode.

Advantageous Effects of Invention

In the present disclosure, the upper resist is thermally shrunk byperforming baking, so that the eave portion of the upper resist is bentupward. This tapers the side wall of the upper resist, so that the metalfilm can be formed on the side wall of the upper resist without stepdisconnection. It is therefore possible to stably prevent a metal fromspilling over in the liftoff process.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional diagram illustrating a method formanufacturing a semiconductor device according to Embodiment 1.

FIG. 2 is a cross-sectional diagram illustrating a method formanufacturing a semiconductor device according to Embodiment 1.

FIG. 3 is a cross-sectional diagram illustrating a method formanufacturing a semiconductor device according to Embodiment 1.

FIG. 4 is a cross-sectional diagram illustrating a method formanufacturing a semiconductor device according to Embodiment 1.

FIG. 5 is a cross-sectional diagram illustrating a method formanufacturing a semiconductor device according to Embodiment 1.

FIG. 6 is a cross-sectional diagram illustrating a method formanufacturing a semiconductor device according to Embodiment 1.

FIG. 7 is a cross-sectional diagram illustrating a modified example ofthe method for manufacturing a semiconductor device according toEmbodiment 1.

FIG. 8 is a cross-sectional diagram illustrating a modified example ofthe method for manufacturing a semiconductor device according toEmbodiment 1.

FIG. 9 is a cross-sectional diagram illustrating a method formanufacturing a semiconductor device according to Embodiment 2.

FIG. 10 is a cross-sectional diagram illustrating a method formanufacturing a semiconductor device according to Embodiment 2.

FIG. 11 is a cross-sectional diagram illustrating a method formanufacturing a semiconductor device according to Embodiment 2.

FIG. 12 is a cross-sectional diagram illustrating a method formanufacturing a semiconductor device according to Embodiment 2.

FIG. 13 is a cross-sectional diagram illustrating a method formanufacturing a semiconductor device according to Embodiment 2.

FIG. 14 is a cross-sectional diagram illustrating a method formanufacturing a semiconductor device according to Embodiment 2.

FIG. 15 is a cross-sectional diagrams illustrating a method formanufacturing a semiconductor device according to Embodiment 3.

FIG. 16 is a cross-sectional diagrams illustrating a method formanufacturing a semiconductor device according to Embodiment 3.

FIG. 17 is a cross-sectional diagrams illustrating a method formanufacturing a semiconductor device according to Embodiment 3.

FIG. 18 is a cross-sectional diagrams illustrating a method formanufacturing a semiconductor device according to Embodiment 3.

FIG. 19 is a cross-sectional diagrams illustrating a method formanufacturing a semiconductor device according to Embodiment 3.

FIG. 20 is a cross-sectional diagrams illustrating a method formanufacturing a semiconductor device according to Embodiment 3.

FIG. 21 is a cross-sectional diagrams illustrating a method formanufacturing a semiconductor device according to Embodiment 3.

FIG. 22 is a cross-sectional diagram illustrating a method formanufacturing a semiconductor device according to Embodiment 4.

FIG. 23 is a cross-sectional diagram illustrating a method formanufacturing a semiconductor device according to Embodiment 4.

FIG. 24 is a cross-sectional diagram illustrating a method formanufacturing a semiconductor device according to Embodiment 4.

FIG. 25 is a cross-sectional diagram illustrating a method formanufacturing a semiconductor device according to Embodiment 4.

FIG. 26 is a cross-sectional diagram illustrating a method formanufacturing a semiconductor device according to Embodiment 4.

FIG. 27 is a cross-sectional diagram illustrating a method formanufacturing a semiconductor device according to Embodiment 4.

FIG. 28 is a cross-sectional diagram illustrating a method formanufacturing a semiconductor device according to Embodiment 4.

FIG. 29 is a cross-sectional diagram illustrating a method formanufacturing a semiconductor device according to Embodiment 4.

FIG. 30 is a cross-sectional diagram illustrating a method formanufacturing a semiconductor device according to Embodiment 4.

FIG. 31 is a cross-sectional diagram illustrating a method formanufacturing a semiconductor device according to Embodiment 5.

FIG. 32 is a cross-sectional diagram illustrating a method formanufacturing a semiconductor device according to Embodiment 5.

FIG. 33 is a cross-sectional diagram illustrating a method formanufacturing a semiconductor device according to Embodiment 5.

FIG. 34 is a cross-sectional diagram illustrating a method formanufacturing a semiconductor device according to Embodiment 5.

DESCRIPTION OF EMBODIMENTS

A method for manufacturing a semiconductor device according to theembodiments of the present disclosure will be described with referenceto the drawings. The same components will be denoted by the samesymbols, and the repeated description thereof may be omitted.

Embodiment 1

FIG. 1 to FIG. 6 are cross-sectional diagrams illustrating a method formanufacturing a semiconductor device according to Embodiment 1. First,as illustrated in FIG. 1, a lower resist 2 is applied on a semiconductorsubstrate 1 formed with a compound semiconductor. The lower resist 2 isa resist for forming an undercut, which is soluble in tetramethylammonium hydroxide (TMAH). For example, LOR series (trade name)manufactured by Nippon Kayaku Co., Ltd. is used as the lower resist 2.The semiconductor substrate 1 and the lower resist 2 are pre-baked at atemperature from 140° C. to 180° C. to vaporize a solvent contained inthe lower resist 2.

Then, as illustrated in FIG. 2, an upper resist 3 is applied on thelower resist 2. The upper resist 3 is a positive type photoresist. Thesemiconductor substrate 1, the lower resist 2 and the upper resist 3 arepre-baked at a temperature from 90° C. to 100° C. As a result, a solventcontained in the upper resist 3 is vaporized. The upper resist 3 ispreferably a high-resolution resist to form a fine pattern. For example,AR5300 (trade name) manufactured by Tokyo Ohka Kogyo Co., Ltd. is usedas the upper resist 3. The upper resist 3 has a film thickness ofapproximately 0.3 μm.

Next, the upper resist 3 is exposed using a mask. The exposure isperformed using an exposure device such as an i-line stepper whichutilizes light having a wavelength of 365 nm. Post exposure baking isperformed at 110° C. Then, the upper resist 3 is developed with analkaline developer to form a first opening 4 NMD-3 (trade name), or thelike, manufactured by Tokyo Ohka Kogyo Co., Ltd. which is TMAH whoseconcentration is 2.38% is used as the alkaline developer.

Upon this development, the lower resist 2 is also dissolved with thedeveloper to form a second opening 5 below the first opening 4. Here,the lower resist 2 is more soluble in the developer than the upperresist 3, so that a width of the second opening 5 of the lower resist 2becomes wider than a width of the first opening 4 of the upper resist 3.As a result, as illustrated in FIG. 3, a resist pattern 6 in a shape ofan eave having an undercut is formed. An eave portion 7 of the upperresist 3 protrudes above the second opening 5 of the lower resist 2. Anupper surface of the semiconductor substrate 1 is exposed at the secondopening 5.

Next, as illustrated in FIG. 4, post baking is performed at atemperature from 100° C. to 120° C. to thermally shrink the upper resist3 so that the eave portion 7 of the upper resist 3 is bent upward. Bythis means, a side wall of the upper resist 3 is tapered. A taper anglecan be adjusted within a range from 30° to 90° by a post-bakingtemperature.

Next, as illustrated in FIG. 5, a metal film 8 is formed on the resistpattern 6 and on the semiconductor substrate 1 exposed at the secondopening 5 through deposition or sputtering. Then, as illustrated in FIG.6, the resist pattern 6 and the metal film 8 on the resist pattern 6 areremoved through liftoff, while the metal film 8 on the semiconductorsubstrate 1 is left as an electrode 9. For example, the electrode 9 is agate electrode. Subsequently, a source electrode, a drain electrode, andthe like, are formed on the semiconductor substrate 1.

As described above, in the present embodiment, the upper resist 3 isthermally shrunk by performing baking, so that the eave portion 7 of theupper resist 3 is bent upward. This tapers the side wall of the upperresist 3, so that the metal film 8 can be formed on the side wall of theupper resist 3 without step disconnection. It is therefore possible tostably prevent a metal from spilling over in the liftoff process.Further, it is possible to easily control a taper angle with apost-baking temperature. The upper resist 3 is bent upward, so that itis possible to make a thickness of the lower resist 2 thinner than athickness of the metal film 8.

FIG. 7 and FIG. 8 are cross-sectional diagrams illustrating a modifiedexample of the method for manufacturing a semiconductor device accordingto Embodiment 1. As illustrated in FIG. 7, an insulating film 10 isformed on the semiconductor substrate 1, and the resist pattern 6 andthe metal film 8 are formed in a similar manner to Embodiment 1. Then,as illustrated in FIG. 8, the resist pattern 6 and the metal film 8 onthe resist pattern 6 are removed through liftoff, so that the metal film8 on the insulating film 10 is left as an electrode 9. The insulatingfilm 10 located in a portion other than below the electrode 9 isremoved. For example, the electrode 9 is a gate electrode, and theinsulating film 10 is a gate insulating film. Other configurations aresimilar to the configurations in Embodiment 1. Also in this case, it ispossible to provide effects of Embodiment 1. Further, in place of theinsulating film 10, the metal film may be formed on the semiconductorsubstrate 1, and the resist pattern 6 and the electrode 9 may be formedon the metal film.

Embodiment 2

FIG. 9 to FIG. 14 are cross-sectional diagrams illustrating a method formanufacturing a semiconductor device according to Embodiment 2.First, asillustrated in FIG. 9, the upper resist 3 is applied on thesemiconductor substrate 1 formed with a compound semiconductor. Theupper resist 3 is a positive type photoresist. The semiconductorsubstrate 1 and the upper resist 3 are pre-baked at a temperature from90° C. to 100° C. to vaporize a solvent contained in the upper resist 3.

Next, as illustrated in FIG. 10, an opening 11 is formed at the upperresist 3 through exposure and development. Then, as illustrated in FIG.11, the semiconductor substrate 1 is isotropically etched using asulfuric acid etchant or a tartaric acid etchant using the upper resist3 at which the opening 11 is formed as a mask, to form a recess 12. Therecess 12 has a wider width than a width of the opening 11 of the upperresist 3. As a result, an undercut in which the eave portion 7 of theupper resist 3 protrudes above the recess 12 is formed.

Next, as illustrated in FIG. 12, post-baking is performed at atemperature from 100° C. to 120° C. to thermally shrink the upper resist3 so that the eave portion 7 of the upper resist 3 is bent upward. Bythis means, the side wall of the upper resist 3 is tapered. A taperangle can be adjusted in a range from 30° to 90° by a post-bakingtemperature.

Next, as illustrated in FIG. 13, the metal film 8 is formed on the upperresist 3 and on a bottom surface of the recess 12 through deposition orsputtering. Then, as illustrated in FIG. 14, the upper resist 3 and themetal film 8 on the upper resist 3 are removed through liftoff, whilethe metal film 8 on the bottom surface of the recess 12 is left as anelectrode 9.

As described above, in the present embodiment, baking is performed tothermally shrink the upper resist 3, so that the eave portion 7 of theupper resist 3 is bent upward. By this means, the side wall of the upperresist 3 is tapered, so that the metal film 8 can be formed on the sidewall of the upper resist 3 without step disconnection. It is thereforepossible to stably prevent a metal from spilling over in the liftoffprocess. Further, it is possible to easily control a taper angle with apost-baking temperature. The upper resist 3 is bent upward, so that itis possible to make a depth of etching of the recess 12 thinner than athickness of the metal film 8.

Embodiment 3

FIG. 15 to FIG. 21 are cross-sectional diagrams illustrating a methodfor manufacturing a semiconductor device according to Embodiment 3.First, as illustrated in FIG. 15, an insulating film 13 is formed on thesemiconductor substrate 1 formed with a compound semiconductor throughCVD (chemical vapor deposition). The insulating film 13 is SiN, SiO, orthe like.

Next, as illustrated in FIG. 16, an upper resist 3 is applied on theinsulating film 13. The upper resist 3 is a positive type photoresist.The semiconductor substrate 1, the insulating film 13 and the upperresist 3 are pre-baked at a temperature from 90° C. to 100° C. tovaporize a solvent contained in the upper resist 3. A first opening 4 isformed at the upper resist 3 through exposure and development.

Next, as illustrated in FIG. 17, the semiconductor substrate 1 issubjected to dry etching through ICP (reactive ion etching), or thelike, using the upper resist 3 at which the first opening 4 is formed asa mask to form a second opening 5 below the first opening 4. The secondopening 5 has a wider width than a width of the first opening 4. As aresult, an undercut in which the eave portion 7 of the upper resist 3protrudes above the second opening 5 is formed.

Next, as illustrated in FIG. 18, post-baking is performed at atemperature from 100° C. to 120° C. to thermally shrink the upper resist3 so that the eave portion 7 of the upper resist 3 is bent upward. Bythis means, the side wall of the upper resist 3 is tapered. A taperangle can be adjusted within a range from 30° to 90° by a post-bakingtemperature.

Next, as illustrated in FIG. 19, the metal film 8 is formed on the upperresist 3 and on the semiconductor substrate 1 exposed at the secondopening 5 through deposition or sputtering. Then, as illustrated in FIG.20, the upper resist 3 and the metal film 8 on the upper resist 3 areremoved through liftoff. As illustrated in FIG. 21, the insulating film13 is removed through BHF (buffered hydrogen fluoride), or the like. Themetal film 8 on the semiconductor substrate 1 is left as an electrode 9.

As described above, in the present embodiment, baking is performed tothermally shrink the upper resist 3, so that the eave portion 7 of theupper resist 3 is bent upward. By this means, the side wall of the upperresist 3 is tapered, so that the metal film 8 can be formed on the sidewall of the upper resist 3 without step disconnection. It is thereforepossible to stably prevent a metal from spilling over in the liftoffprocess. Further, it is possible to easily control a taper angle by apost-baking temperature. The upper resist 3 is bent upward, so that itis possible to make a thickness of the insulating film 13 thinner than athickness of the metal film 8.

Embodiment 4

FIG. 22 to FIG. 30 are cross-sectional diagrams illustrating a methodfor manufacturing a semiconductor device according to Embodiment 4.First, as illustrated in FIG. 22, a lower resist 2 is applied on thesemiconductor substrate 1. The lower resist 2 is a resist for forming anundercut which is soluble in TMAH. The semiconductor substrate 1 and thelower resist 2 are pre-baked at a temperature from 140° C. to 180° C. tovaporize a solvent contained in the lower resist 2.

Next, as illustrated in FIG. 23, an upper resist 14 which is an imagereversal resist is applied on the lower resist 2. For example, imagereversal resist AZ5214E (trade name) manufactured by Merck PerformanceMaterials Ltd. can be used as the upper resist 14. The upper resist 14has a film thickness of approximately 1.0 μm.

Next, as illustrated in FIG. 24, a second region 14 b of the upperresist 14 is exposed while preventing a first region 14 a of the upperresist 14 from being exposed by covering the first region 14 a with amask 15. The exposure is performed using an exposure device such as ani-line stepper which utilizes a light having a wavelength of 365 nm. Afree acid is generated in the exposed second region 14 b of the upperresist 14.

Next, as illustrated in FIG. 25, a shrink agent 16 which reacts with thefree acid in the resist is applied on the upper resist 14. For example,shrink agent AZ R200 (trade name) manufactured by Merck PerformanceMaterials Ltd., is used as the shrink agent 16.

Note that AZ R200 is typically used as a pattern shrink. An acid isgenerated as a result of a novolak resist being exposed, and an exposureportion is developed through alkaline development, so that an openingportion is formed. A residual acid is generated at the opening portion.By applying the shrink agent and performing baking, cross-linkingreaction with the residual acid occurs, and by removing the shrink agentthrough water washing, the opening portion can be made smaller. Theshrink agent is water-soluble, and a shrink portion is alkaline-soluble.In the present embodiment, the shrink agent is not used to make theopening portion smaller.

Next, as illustrated in FIG. 26, baking is performed at 110° C. Thebaking is performed both for reversal baking of the upper resist 14 andfor shrink baking of the shrink agent. The baking causes cross-linkingreaction between the free acid in a resist upper portion 14 b 1 of theexposed second region 14 b of the upper resist 14 and the shrink agent16. In this event, thermal cross-linking reaction of the free acid of aresist lower portion 14 b 2 of the second region 14 b occurs by featuresof the image reversal resist. By this means, the resist upper portion 14b 1 becomes soluble in the developer, and the resist lower portion 14 b2 becomes insoluble in the developer.

Next, as illustrated in FIG. 27, a free acid is generated in the firstregion 14 a of the upper resist 14 by the whole surface being exposed,and the first region 14 a becomes alkaline-soluble. Then, development isperformed using an alkaline developer, the water-soluble shrink agent16, the resist upper portion 14 b 1 of the second region 14 b and thefirst region 14 a of the upper resist 14 are removed to form a firstopening 4 at the upper resist 14. NMD-3(trade name), or the like,manufactured by Tokyo Ohka Kogyo Co., Ltd. which is TMAH whoseconcentration is 2.38% can be used as the alkaline developer.

Upon the development, the lower resist 2 is also dissolved with thedeveloper to form a second opening 5 below the first opening 4. Here,the lower resist 2 is more soluble in the developer than the upperresist 14, so that a width of the second opening 5 of the lower resist 2becomes wider than a width of the first opening 4 of the upper resist14. As a result, as illustrated in FIG. 28, a resist pattern 6 in ashape of an eave having an undercut is formed. An eave portion 7 of theupper resist 14 protrudes above the second opening 5 of the lower resist2. An upper surface of the semiconductor substrate 1 is exposed at thesecond opening 5.

Next, as illustrated in FIG. 29, a metal film 8 is formed on the upperresist 14 and on the semiconductor substrate 1 exposed at the secondopening 5 through deposition or sputtering. Then, as illustrated in FIG.30, the upper resist 14, the metal film 8 on the upper resist 14 and thelower resist 2 are removed through liftoff, while the metal film 8 onthe semiconductor substrate 1 is left as an electrode 9.

As described above, in the present embodiment, the side wall of theupper resist 14 is tapered by using the shrink agent 16 which reactswith an acid generated in the upper resist 14. By this means, it ispossible to form the metal film 8 on the side wall of the upper resist14 without step disconnection. A film thickness of the upper resist 14after pattern formation can be made thinner than a film thickness whenthe upper resist 14 is applied, so that a metal to be formed on the sidewall of the upper resist 14 decreases. It is therefore possible tostably prevent a metal from spilling over in the liftoff process.

Further, while a fine pattern cannot be formed due to an opening sizebeing larger in Embodiments 1 to 3, the present embodiment enables afine pattern to be formed. Note that an insulating film may be formed onthe semiconductor substrate 1, and the lower resist 2, the electrode 9,and the like, may be formed on the insulating film.

Embodiment 5

FIG. 31 to FIG. 34 are cross-sectional diagrams illustrating a methodfor manufacturing a semiconductor device according to Embodiment 5.First, process from FIG. 22 to FIG. 28 in Embodiment 4 is performed,and, as illustrated in FIG. 31, the upper resist 14 is tapered to form aresist pattern 6 in a shape of an eave having an undercut.

Next, as illustrated in FIG. 32, post-baking is performed at atemperature from 100° C. to 120° C. to thermally shrink the upper resist14, so that the eave portion 7 of the upper resist 14 is bent upward. Bythis means, the side wall of the upper resist 14 is further tapered. Thetaper angle can be adjusted in a range from 30° to 90° by a post-bakingtemperature.

Next, as illustrated in FIG. 33, the metal film 8 is formed on the upperresist 14 and on the bottom surface of the recess 12 through depositionor sputtering. Then, as illustrated in FIG. 34, the resist pattern 6 andthe metal film 8 on the resist pattern 6 are removed through liftoff,while the metal film 8 on the semiconductor substrate 1 is left as anelectrode 9.

As described above, in the present embodiment, baking is performed tothermally shrink the upper resist 14, so that the eave portion 7 of theupper resist 14 is bent upward. By this means, the side wall of theupper resist 14 is more tapered than the side wall of Embodiment 4, sothat the metal film 8 can be formed on the side of the upper resist 14without step disconnection. It is therefore possible to stably prevent ametal from spilling over in the liftoff process. Further, it is possibleto easily control a taper angle by a post-baking temperature. Otherconfigurations and effects are similar to those in Embodiment 4.

REFERENCE SIGNS LIST

-   1 semiconductor substrate;-   2 lower resist;-   3 upper resist;-   4 first opening;-   5 second opening;-   6 resist pattern;-   7 eave portion;-   8 metal film;-   9 electrode;-   10 insulating film;-   11 opening;-   12 recess;-   13 insulating film;-   14 upper resist;-   14 a first region;-   14 b second region;-   14 b 1 resist upper portion;-   14 b 2 resist lower portion;-   15 mask;-   16 shrink agent

1. A method for manufacturing a semiconductor device comprising:applying a lower resist on a semiconductor substrate; applying an upperresist on the lower resist; forming a first opening in the upper resistby exposure and development and dissolving the lower resist with adeveloper upon the development to form a second opening having a widthwider than that of the first opening below the first opening so that aresist pattern in a shape of an eave having an undercut is formed;performing baking to thermally shrink the upper resist to bent an eaveportion of the upper resist upward so that a taper angle is in a rangefrom 30° to 90°; after the baking, forming a metal film on the resistpattern and on the semiconductor substrate exposed at the secondopening; and removing the resist pattern and the metal film on theresist pattern and leaving the metal film on the semiconductor substrateas an electrode.
 2. The method for manufacturing a semiconductor deviceaccording to claim 1, further comprising forming an insulating film onthe semiconductor substrate, wherein the resist pattern and theelectrode are formed on the insulating film.
 3. A method formanufacturing a semiconductor device comprising: applying a resist on asemiconductor substrate; forming an opening in the resist by exposureand development; isotropically etching the semiconductor substrate usingthe resist at which the opening is formed as a mask, to form a recesshaving a wider width than a width of the opening; performing baking tothermally shrink the resist to bent an eave portion of the resist upwardso that a taper angle is in a range from 30° to 90°; after the baking,forming a metal film on the resist and on a bottom surface of therecess; and removing the resist and the metal film on the resist andleaving the metal film on the bottom surface of the recess as anelectrode.
 4. A method for manufacturing a semiconductor devicecomprising: forming an insulating film on a semiconductor substrate;applying a resist on the insulating film; forming a first opening in theresist by exposure and development; isotropically etching the insulatingfilm using the resist at which the first opening is formed as a mask toform a second opening having a width wider than that of the firstopening below the first opening; performing baking to thermally shrinkthe resist to bent an eave portion of the resist upward so that a taperangle is in a range from 30° to 90°; after the baking, forming a metalfilm on the resist and on the semiconductor substrate exposed at thesecond opening; and removing the resist, the metal film on the resist,and the insulating film and leaving the metal film on the semiconductorsubstrate as an electrode.
 5. A method for manufacturing a semiconductordevice comprising: applying a lower resist on a semiconductor substrate;applying an upper resist which is an image reversal resist on the lowerresist; preventing a first region of the upper resist from being exposedby covering the first region with a mask and exposing a second region ofthe upper resist; after exposing the second region, applying a shrinkagent on the upper resist; performing baking to cause cross-linkingreaction between free acid in a resist upper portion of the secondregion and the shrink agent and to cause thermal cross-linking reactionof free acid in a resist lower portion of the second region; after thebaking, exposing the first region by whole surface exposure; after thewhole surface exposure, removing the shrink agent, the resist upperportion of the second region and the first region of the upper resist bydevelopment to form a first opening and dissolving the lower resist witha developer upon the development to form a second opening having a widthwider than that of the first opening below the first opening so that aresist pattern in a shape of an eave having an undercut is formed;forming a metal film on the resist pattern and on the semiconductorsubstrate exposed at the second opening; and removing the resist patternand the metal film on the resist pattern and leaving the metal film onthe semiconductor substrate as an electrode.
 6. The method formanufacturing a semiconductor device according to claim 5, furthercomprising, after forming the resist pattern and before forming themetal film, performing baking to thermally shrink the upper resist tobent an eave portion of the upper resist upward.